# QC Horsepower and possible Compiler problems

**URL:** <https://unity.neuraldsp.com/t/qc-horsepower-and-possible-compiler-problems/2817>\
**Category:** Quad Cortex\
**Created:** [September 5, 2020, 12:44pm UTC](https://unity.neuraldsp.com/t/qc-horsepower-and-possible-compiler-problems/2817 "2020-09-05T12:44:21Z")\
**Posts on this page:** 5\
**Page:** 1

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**Author:** ![lpauls56](https://avatars.discourse-cdn.com/v4/letter/l/8491ac/32.png) [@lpauls56](https://unity.neuraldsp.com/u/lpauls56)\
**Post date:** [September 5, 2020, 12:44pm UTC](https://unity.neuraldsp.com/t/qc-horsepower-and-possible-compiler-problems/2817/1 "2020-09-05T12:44:21Z")

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Doug Castro  
How does/will the two Sharc Chips stack up against the Fractal FM3 / AXE 3  
I understand that the compiler for the Sharc has some issues that significantly decreases the horsepower and is quite a bit less than the advertised numbers would suggest.

Thanks

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**Author:** ![sean.page](https://avatars.discourse-cdn.com/v4/letter/s/b4bc9f/32.png) [@sean.page](https://unity.neuraldsp.com/u/sean.page)\
**Post date:** [September 5, 2020, 1:19pm UTC](https://unity.neuraldsp.com/t/qc-horsepower-and-possible-compiler-problems/2817/2 "2020-09-05T13:19:50Z")

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The compiler issue does not reduce horsepower  
The issue was the way Fractal writes the coding the compiler translates that code  
For FAS it understood most of the code but missed things thats why it was hard to fix  
Neural may never have this issue at all

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**Author:** ![lpauls56](https://avatars.discourse-cdn.com/v4/letter/l/8491ac/32.png) [@lpauls56](https://unity.neuraldsp.com/u/lpauls56)\
**Post date:** [September 5, 2020, 1:49pm UTC](https://unity.neuraldsp.com/t/qc-horsepower-and-possible-compiler-problems/2817/3 "2020-09-05T13:49:24Z")

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Thanks for the response Sean :  
I was thinking that the Fractal coding was done in such a way that it’s coded efficiency would  
help “maximize” the two Sharc cores DSP power. Therefore having to change the coding for the compiler would reduce it’s performance/power.

Larry

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**Author:** ![March](https://avatars.discourse-cdn.com/v4/letter/m/858c86/32.png) [@March](https://unity.neuraldsp.com/u/March)\
**Post date:** [January 10, 2021, 4:03pm UTC](https://unity.neuraldsp.com/t/qc-horsepower-and-possible-compiler-problems/2817/4 "2021-01-10T16:03:21Z")

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isn’t it 4 sharc Core?

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**Author:** ![lpauls56](https://avatars.discourse-cdn.com/v4/letter/l/8491ac/32.png) [@lpauls56](https://unity.neuraldsp.com/u/lpauls56)\
**Post date:** [January 10, 2021, 4:34pm UTC](https://unity.neuraldsp.com/t/qc-horsepower-and-possible-compiler-problems/2817/5 "2021-01-10T16:34:38Z")

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Yes 2 per chip.  
AFAIK there is no compiler problem and there has been none mentioned anywhere.